View MAX9311_192851.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2078; Rev 2; 10/02
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
General Description
The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept singleended inputs by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9311/MAX9313 feature low part-to-part skew (30ps) and output-to-output skew (12ps), making them ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The MAX9311 features an on-chip VBB reference output of 1.425V below the positive supply voltage. The MAX9313 offers an on-chip V BB reference output of 1.32V below the positive supply voltage. Both devices are offered in space-saving, 32-pin 5mm 5mm TQFP, 5mm x 5mm QFN, and industry-standard 32-pin 7mm x 7mm LQFP packages.
Features
o +2.25V to +3.8V Differential HSTL/LVPECL Operation o -2.25V to -3.8V LVECL Operation o 30ps (typ) Part-to-Part Skew o 12ps (typ) Output-to-Output Skew o 312ps (typ) Propagation Delay o 300mV Differential Output at 3GHz o On-Chip Reference for Single-Ended Inputs o Output Low with Open Input o Pin Compatible with MC100LVEP111 (MAX9311) and MC100EP111 (MAX9313) o Offered in Tiny QFN* Package (70% Smaller Footprint than LQFP)
MAX9311/MAX9313
Ordering Information
PART MAX9311ECJ MAX9311EGJ* MAX9311EHJ* MAX9313ECJ MAX9313EGJ* MAX9313EHJ* TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 32 LQFP (7mm 7mm) 32 QFN (5mm 5mm) 32 TQFP (5mm 5mm) 32 LQFP (7mm 7mm) 32 QFN (5mm 5mm) 32 TQFP (5mm 5mm)
Applications
Precision Clock Distribution Low-Jitter Data Repeater
*Future product--contact factory for availability.
Pin Configuration
TOP VIEW
VCC Q0 32 31 Q0 30 Q1 29 Q1 28 Q2 27 Q2 26 VCC 25
VCC CLKSEL CLK0 CLK0 VBB CLK1 CLK1 VEE
1 2 3 4 5 6 7 8 9 10 11 Q9 12 Q8 13 Q8 14 Q7 15 Q7 16 VCC
24 Q3 23 Q3 22 Q4 21 Q4 LQFP (7mm x 7mm), TQFP (5mm x 5mm), QFN (NO LEADS EXTENDING FROM QFN PACKAGE) MAX9311/MAX9313 CLKSEL 0 19 Q5 18 Q6 17 Q6 1 CLK0, CLK0 CLK1, CLK1 ON OFF OFF ON
MAX9311 MAX9313
20 Q5
VCC Q9
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
ABSOLUTE MAXIMUM RATINGS
VCC - VEE...............................................................................4.1V Inputs (CLK_, CLK_, CLKSEL)..............VEE - 0.3V to VCC + 0.3V CLK_ to CLK_ ....................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................0.65mA Junction-to-Ambient Thermal Resistance in Still Air 7mm x 7mm LQFP .....................................................+90C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 7mm x 7mm LQFP .....................................................+60C/W Junction-to-Case Thermal Resistance 7mm x 7mm LQFP .....................................................+12C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (CLKSEL, CLK_, CLK_, Q_, Q_, VBB).......................................................................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS -40C MIN VCC - 1.23 VCC - 1.165 VEE VEE MAX MIN VCC - 1.23 VCC - 1.165 VEE VEE +25C MAX MIN VCC - 1.23 VCC - 1.165 VEE VEE +85C MAX UNITS
SINGLE-ENDED INPUT (CLKSEL) Input High Voltage Internal VBB threshold MAX9311 MAX9313 MAX9311 MAX9313 VCC VCC VCC - 1.62 VCC - 1.475 150 -10 +10 -10 VCC VCC VCC - 1.62 VCC - 1.475 150 +10 -10 VCC V VCC VCC - 1.62 VCC - 1.475 150 +10 A A
VIH
Input Low Voltage
VIL
Internal VBB threshold
V
Input High Current Input Low Current
IIH IIL
DIFFERENTIAL INPUTS (CLK_, CLK_) VBB connected MAX9311 to CLK_ (VIL for VBB connected MAX9313 to CLK_), Figure 1 VCC - 1.23 VCC VCC - 1.23 VCC VCC - 1.23 VCC V VCC - 1.165 VCC VCC - 1.165 VCC VCC - 1.165 VCC
Single-Ended Input High Voltage
VIH
2
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS VBB connected MAX9311 to CLK_ (VIH for VBB connected MAX9313 to CLK_), Figure 1 -40C MIN VEE MAX VCC - 1.62 VCC - 1.475 MIN VEE +25C MAX VCC - 1.62 VCC - 1.475 MIN VEE +85C MAX VCC -1.62 V VEE VEE VEE VCC -1.475 UNITS
MAX9311/MAX9313
Single-Ended Input Low Voltage
VIL
High Voltage of Differential Input Low Voltage of Differential Input Differential Input Voltage Input High Current CLK_ Input Low Current CLK_ Input Low Current OUTPUTS (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage REFERENCE (VBB) Reference Voltage Output (Note 5) POWER SUPPLY Supply Current (Note 6)
VIHD
VEE +1.2
VCC
VEE + 1.2
VCC
VEE +1.2
VCC
V
VILD
VEE
VCC - 0.095 VCC - VEE 3.0 150
VEE
VCC - 0.095 VCC - VEE 3.0 150
VEE
VCC - 0.095 VCC - VEE 3.0 150
V
VIHD VILD
For VCC - VEE < 3.0V For VCC - VEE 3.0V
0.095 0.095
0.095 0.095
0.095 0.095
V
IIH IILCLK IILCLK -10 -150
A A A
+10
-10 -150
+10
-10 -150
+10
VOH
Figure 1
VCC - 1.025
VCC - 0.900
VCC - 1.025
VCC - 0.900
VCC - 1.025
VCC - 0.900
V
VOL VOH VOL
Figure 1
VCC - 1.93 670
VCC - 1.695 950
VCC - 1.93 670
VCC - 1.695 950
VCC - 1.93 670
VCC - 1.695 950
V
Figure 1
mV
MAX9311 VBB IBB = 0.5mA MAX9313
VCC - 1.525 VCC - 1.38
VCC - 1.325 VCC - 1.26
VCC - 1.525 VCC - 1.38
VCC - 1.325 VCC - 1.26
VCC - 1.525 VCC - 1.38
VCC - 1.325 V VCC - 1.26
IEE
75
82
95
mA
_______________________________________________________________________________________
3
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.25V to 3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), CLKSEL = high or low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC -1V, VILD = VCC -1.5V.) (Note 7)
PARAMETER Differential Input-toOutput Delay Output-toOutput Skew (Note 8) Part-to-Part Skew (Note 9) Added Random Jitter (Note 10) Added Deterministic Jitter (Note 10) SYMBOL CONDITIONS tPLHD, tPHLD -40C MIN 220 TYP 321 MAX 380 MIN 220 +25C TYP 312 MA 410 MIN 260 +85C TYP 322 MAX 400 UNITS
Figure 2
ps
tSKOO
12
46
12
46
10
35
ps
tSKPP fIN = 1.5GHz, Clock pattern tRJ fIN = 3.0GHz, Clock pattern 3Gbps, 223 -1 PRBS pattern VOH - VOL 350mV, Clock pattern, Figure 2 fMAX VOH - VOL 500mV, Clock pattern, Figure 2
30 1.2 1.2
160 2.5 2.6
30 1.2 1.2
190 2.5 2.6
30 1.2 1.2
140 2.5
ps
ps (RMS) 2.6 ps (p-p)
tDJ
80
95
80
95
80
95
2.0
2.0
3.0
2.0 GHz
Switching Frequency
1.5
1.5
1.5
Output Rise/Fall Time (20% to 80%)
tR , t F
Figure 2
100
112
140
100
116
140
100
121
140
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V for the MAX9311 and VCC - VEE = 2.7V to 3.8V for the MAX9313. Note 4: DC parameters production tested at TA = +25C. Guaranteed by design and characterization over the full operating temperature range. Note 5: Use VBB only for inputs that are on the same device as the VBB reference. Note 6: All pins open except VCC and VEE. Note 7: Guaranteed by design and characterization. Limits are set at 6 sigma. Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 10:Device jitter added to the input signal.
4
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
Typical Operating Characteristics
(VCC = +3.3V, VEE = 0, VIHD = VCC - 0.95V, VILD = VCC - 1.25V, input transition time = 125ps (20% to 80%), fIN = 1.5GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9311 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9311 toc02
TRANSITION TIME vs. TEMPERATURE
MAX9311 toc03
85 80 SUPPLY CURRENT (mA) 75 70 65 60 55 50 -40 -15 10 35 60
0.9 0.8 OUTPUT AMPLITUDE (V) 0.7 0.6 0.5 0.4 0.3 0.2
130 125 TRANSITION TIME (ps) 120 115 tF 110 105
tR
0.1 0 85 0 1000 2000 3000 TEMPERATURE (C) FREQUENCY (MHz) 100 -40 -15 10 35 60 85 TEMPERATURE (C)
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9311 toc04
PROPAGATION DELAY vs. TEMPERATURE
340 PROPAGATION DELAY (ps) tPLHD 320 300 280 260 240 220 200 VIHD = VCC - 0.95V VILD = VCC - 1.1V tPHLD
MAX9311 toc05
313 312 PROPAGATION DELAY (ps) 311 310 309 308 307 306 305 304 303 1.0 1.4 1.8 2.2 2.6 3.0 3.4 tPHLD tPLHD VIHD - VILD = 150mV
360
3.8
-40
-15
10
35
60
85
VIHD (V)
TEMPERATURE (C)
_______________________________________________________________________________________
5
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
Pin Description
PIN 1, 9, 16, 25, 32 2 3 4 5 6 7 8 10 11 12 13 14 15 17 18 19 20 21 22 23 24 26 27 28 29 30 31 NAME VCC FUNCTION Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Clock Select Input (Single-Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1, CLK1 input. The CLKSEL threshold is VBB. If CLKSEL is not driven by a logic signal, use a 1k pulldown to VEE to select CLK0, CLK0, or a 1k pullup to VCC to select CLK1, CLK1. Noninverting Differential Clock Input 0. Internal 75k pulldown resistor. Inverting Differential Clock Input 0. Internal 75k pullup and pulldown resistors. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise, leave open. Noninverting Differential Clock Input 1. Internal 75k pulldown resistor. Inverting Differential Clock Input 1. Internal 75k pullup and pulldown resistors. Negative Supply Voltage Inverting Q9 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q9 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q8 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q8 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q7 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q7 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q6 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q6 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q5 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q5 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q4 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q4 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V.
CLKSEL CLK0 CLK0 VBB CLK1 CLK1 VEE Q9 Q9 Q8 Q8 Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0
6
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Detailed Description
The MAX9311/MAX9313 are low skew, 1-to-10 differential drivers designed for clock and data distribution. A 2:1 mux selects between the two differential inputs, CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched by the single-ended CLKSEL input. A logic low selects the CLK0, CLK0 input. A logic high selects the CLK1, CLK1 input. The logic threshold for CLKSEL is set by an internal VBB voltage reference. The CLKSEL input can be driven to VCC and VEE or by a single-ended LVPECL/ LVECL signal. The selected input is reproduced at 10 differential outputs. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The differential inputs can be configured to accept single-ended inputs when operating at approximately VCC VEE = +3.0V to +3.8V for the MAX9311 or VCC - VEE = +2.7V to +3.8V for the MAX9313. This is accomplished by connecting the on-chip reference voltage, VBB, to an input as a reference. For example, the differential CLK0, CLK0 input is converted to a noninverting, single-ended input by connecting VBB to CLK0 and connecting the single-ended input to CLK0. Similarly, an inverting input is obtained by connecting VBB to CLK0 and connecting the single-ended input to CLK0. With a differential input configured as single-ended (using V BB), the singleended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal. When a differential input is configured as a single-ended input (using VBB), the approximate supply range is VCC VEE = +3.0V to +3.8V for the MAX9311 and VCC - VEE = +2.7V to +3.8V for the MAX9313. This is because one of the inputs must be VEE + 1.2V or higher for proper operation of the input stage. VBB must be at least VEE + 1.2V because it becomes the high-level input when the other (single-ended) input swings below it. Therefore, minimum VBB = VEE + 1.2V. The minimum VBB output for the MAX9311 is VCC 1.525V and the minimum VBB output for the MAX9313 is VCC - 1.38V. Substituting the minimum VBB output for each device into VBB = VEE + 1.2V results in a minimum supply of 2.725V for the MAX9311 and 2.58V for the MAX9313. Rounding up to standard supplies gives the single-ended operating supply ranges of VCC - VEE = 3.0V to 3.8V for the MAX9311 and VCC - VEE = 2.7V to 3.8V for the MAX9313. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. The VBB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Use VBB only for inputs that are on the same device as the VBB reference. The maximum magnitude of the differential input from CLK_ to CLK_ is 3.0V or VCC - VEE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting inputs (CLK0 and CLK1) are biased with a 75k pullup to VCC and a 75k pulldown to VEE. The noninverting inputs (CLK0 and CLK1) are biased with a 75k pulldown to VEE. The single-ended CLKSEL input does not have a bias resistor. If not driven, pull CLKSEL up or down with a 1kHz resistor (see Pin Description). Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). Output levels are referenced to VCC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are LVPECL. The outputs are LVECL when VCC is connected to GND and VEE is connected to a negative supply. A single-ended input of at least VBB 95mV or a differential input of at least 95mV switches the outputs to the V OH and V OL levels specified in the DC Electrical Characteristics table.
MAX9311/MAX9313
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F value capacitor closest to the device. Use multiple parallel vias for low inductance. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC (if the VBB reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the performance of the MAX9311/MAX9313. Connect each signal of a differential input or output to a 50 characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Reduce skew within a
7
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
differential pair by matching the electrical length of the traces.
Chip Information
TRANSISTOR COUNT: 250
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0.
CLK_ VIH CLK_ VIL VBB
(CONNECTED TO CLK_) VOH VOH - VOL VOL
Q_ Q_
Figure 1. Switching with Single-Ended Input
CLK_ VIHD - VILD CLK_ tPLHD Q_ VOH - VOL Q_ tPHLD
VIHD VILD
VOH VOL
80% 0 (DIFFERENTIAL) (Q_) - (Q_) 20% tR
80% 0 (DIFFERENTIAL) 20% tF
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
8
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Functional Diagram
Q0 Q0 VCC Q1 Q1 Q2 Q2 Q3 75k 75k Q3 VEE VEE VCC Q4 0 Q4 1 Q5 Q5 Q6 Q6 Q7 75k 75k Q7 VEE CLKSEL VBB VEE Q8 Q8 Q9 Q9
MAX9311/MAX9313
75k CLK0 CLK0
75k CLK1 CLK1
_______________________________________________________________________________________
9
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
32L/48L TQFP EPS
10
______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
32L TQFP, 5x5x01.0.EPS
MAX9311/MAX9313
______________________________________________________________________________________
11
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9311/MAX9313
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
32L QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9311

	To Download MAX9311 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .